This invention relates generally to digital electronic circuits and more particularly to status registers having asynchronous resets.
The majority of operations within a digital electronic circuit are synchronous: i.e. the various gates, flip-flops, registers, etc. within the circuit are synchronized by clock pulses generated by a master clock. This synchronization minimizes problems caused by the inherent delay of signals as they flow through the circuit by ensuring that the appropriate input signals are present before a circuit element is activated.
Asynchronous operation occurs when various elements within a circuit are not synchronized to the same clock. As noted in Microcomputer Interfacing, Harold S. Stone, Addison-Wesley Publishing Company, 1983, pp. 108, the only way to be sure that a system is free from clocking difficulties is to use a single master clock from which all other timing is derived. Therefore, asynchronous operation is inherently subject to clocking errors which must be detected and hopefully remedied to ensure the proper operation of the asynchronous circuitry.
An example of a circuit which may exhibit problems associated with asynchronous operation is the conditional status register. A typical asynchronous conditional status register includes a number of input flip-flops which can capture data corresponding to various states within a digital circuit. For example, a particular input flip-flop could be triggered when a particular function within the digital has been completed. The outputs of the input flip-flops are coupled to the inputs of asynchronous output latches and (hopefully) reflect the values of the input flip-flops. However, since the output latches are enabled in an asynchronous fashion (such as by a user request for the values stored in the status register), the values stored in the output latches may not be the same as the values stored in the input flip-flops. This is because it takes a finite time for a signal from the output of a flip-flop to be latched into a corresponding latch. Since the latches are read asynchronously, recent flip-flop values may not yet have been latched into the output latches, in a phenomenon known as a "race condition." In a race condition, data from the flip-flop has not yet traveled to the data input of the latch at the time of the latch enable. This can result in an erroneous "read" of the status register, with possibly dire consequences to the proper operation of the digital system.
In U.S. Pat. No. 5,038,059 of Ebzery et al., a two-stage binary status register is set and reset by independent signals. The status register includes a first stage set-reset (SR) flip-flop, the output of which is connected to a second stage latch circuit. The set signals and reset signals are applied to the two stages in a manner which ensures that the output of the second stage latch always supplies an output corresponding to each set input signal, irrespective of the times of arrival of the set and reset signals, including all conditions of signal overlap and simultaneous arrival of both the set and reset signals.
Ebzery et al. resolve ambiguity problems by setting their status register to a known state in the event of a conflict. This known state is a default which, preferably, is the most common state for the register. While this reduces the problem of erroneous reads, it does not completely eliminate the possibility of the reading of erroneous data from the status register. Furthermore, Ebzery et al. do not provide a method or apparatus for alerting a system to a possible error condition caused by conflicts within the status register.